Through silicon vias filled with planarized carbon nanotube bundles

doi:10.1088/0957-4484/20/48/485203

Through silicon vias filled with planarized carbon nanotube bundles

Teng Wang et al 2009 Nanotechnology 20 485203 (6pp) doi: 10.1088/0957-4484/20/48/485203

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Teng Wang^1,2, Kjell Jeppson¹, Niklas Olofsson³, Eleanor E B Campbell^4,5 and Johan Liu^1,6
¹ Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-412 96 Göteborg Sweden,
² SHT Smart High Tech AB, Nordgårdsvägen 19, SE-428 34 Kållered, Sweden
³ Department of Physics, Göteborg University, SE-412 96 Göteborg, Sweden
⁴ School of Chemistry, Edinburgh University, West Mains Road, Edinburgh EH9 3JJ, UK
⁵ Department of Physics, Konkuk University, Seoul 143-701, Korea
⁶ Key Laboratory of New Displays and System Applications and SMIT Center, School of Mechanical Engineering and Automation, Box 282, No. 149 Yan Chang Road, Yan Chang Campus, Shanghai University, 200072 Shanghai, People's Republic of China
E-mail: johan.liu@chalmers.se

Abstract. The feasibility of using carbon nanotube (CNT) bundles as the fillers of through silicon vias (TSVs) has been demonstrated. CNT bundles are synthesized directly inside TSVs by thermal chemical vapor deposition (TCVD). The growth of CNTs in vias is found to be highly dependent on the geometric dimensions and arrangement patterns of the vias at atmospheric pressure. The CNT–Si structure is planarized by a combined lapping and polishing process to achieve both a high removal rate and a fine surface finish. Electrical tests of the CNT TSVs have been performed and their electrical resistance was found to be in the few hundred ohms range. The reasons for the high electrical resistance have been discussed and possible methods to decrease the electrical resistance have been proposed.

Print publication: Issue 48 (2 December 2009)
Received 30 September 2009, in final form 1 October 2009
Published 4 November 2009

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Through silicon vias filled with planarized carbon nanotube bundles

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