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A reliable scheme for fabricating sub-5 nm co-planar junctions for single-molecule electronics

M S M Saifullah et al 2002 Nanotechnology 13 659-662   doi: 10.1088/0957-4484/13/5/323  Help

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M S M Saifullah1, T Ondarçuhu2, D K Koltsov1, C Joachim2 and M E Welland1
1 Nanoscale Science Laboratory, Department of Engineering, University of Cambridge, Trumpington Street, Cambridge CB2 1PZ, UK
2 CEMES-CNRS, 29 Rue Jeanne Marvig, BP 4347, 31055 Toulouse Cedex, France
E-mail: msms2@eng.cam.ac.uk (M S M Saifullah)

Abstract. We demonstrate a high yield production scheme to fabricate sub-5 nm co-planar metal–insulator–metal junctions. This involves determining the relationship between the actual gap between the metallic junctions for a given designed gap, and the use of weak developers with ultrasonic agitation to process the exposed resist. This results in an improved process to achieve narrow inter-electrode gaps. The gaps were imaged using an AFM equipped with a carbon nanotube tip to achieve a high degree of accuracy in measurement. The smallest gap unambiguously measured was ~ 2 nm. Gaps with ≤ 5 nm spacing were produced with a very high yield of about 75% for a designed inter-electrode distance of 0 nm. The leakage resistance of the gaps was found to be of the order of 1012 Ω. The entire junction structure was designed to be co-planar to better than 1 nm over 1 μ m2.

Print publication: Issue 5 (October 2002)
Received 12 August 2002, in final form 4 September 2002
Published 20 September 2002

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